Super Computing 22 OpenPOWER ADG Workshop

Will summarise the details of workshop agenda

Provide Overview about OpenPOWER foundation and its features

The teaching of the inter-related areas of computer architecture, computer organization, and computer systems is at a crossroads, one that could lead to another pedagogical (r)evolution. The first revolution occurred in the early 1990s, spurred by research in the 1980s that re-visited RISC architectures and resulting in the seminal book entitled "Computer Architecture: A Quantitative Approach" in 1989 and its subsequent prequel book entitled "Computer Organization and Design: The Hardware/Software Interface" in 1993, both centered around the MIPS instruction set architecture (ISA). By the 2000s, many institutions in higher education transitioned their traditional course on operating systems concepts to a hands-on computer systems curriculum based on the CISC x86-64 ISA, as captured by the seminal book entitled "Computer Systems: A Programmer’s Perspective." While these books have served as exemplars for their respective areas, one might argue that the use of disparate ISAs – MIPS versus x86-64 – serves as an unnecessary learning impediment and source of confusion. A potential solution to this problem would be to align the teaching of all these inter-related areas with the MIPS ISA entirely or x86-64 ISA entirely; however, the former has limited real-world deployment while the latter is closed (and unnecessarily complex, i.e., CISC). In contrast, the POWER architecture is open source and enjoys widespread deployment, including two of the fastest supercomputers in the world (i.e., Sierra at Lawrence Livermore National Lab and Summit at Oak Ridge National Lab). For these reasons, we envision a vertically integrated curriculum from hardware to systems software based on the POWER instruction set architecture.

The aim of this presentation and demo to bring together developers and system integrators with an interest in open, secure soft BMC solutions based on the Kestrel and Zephyr / OpenBMC technology stack. We will provide hands-on access to an OpenPOWER platform and associated ECP5-based Arctic Tern module, with primary goals of encouraging developer participation in the overall Kestrel ecosystem as well as adoption of FPGA-based soft BMC technology for secure applications. Feedback will be gathered from other ODMs and system integrators to help tailor the Kestrel stack to existing real-world requirements.

Todd will discuss the LibreBMC project, give a brief overview of the DC-SCM spec, and show a recorded demo of the LibreBMC FPGA booting an IBM AC922 compute node. Discussions on next steps and how to get involved will be had.

Lowering the barriers to chip design using OpenFASOC:
Fully Autonomous System-on-Chip (FASoC) tool is a DARPA-funded project within the IDEA program. Its main objective is to address the need for analog compilers. The framework relies on the place and route digital flow which has long been extensively automated while most analog flows are still extremely reliant on manual design. This lack of analog automation tools leads to long design cycles and costs. FASoC addresses this need and uses a cell-based analog design generation methodology to generate different analog and mixed-signal (AMS) blocks (i.e., PLL, LDO, DC-DC converters, Temperature Sensors, etc.). A few SoCs have been taped out in SkyWater 130-nm, BI-CMOS 130-nm, TSMC 65-nm and Globalfoundries 12-nm. OpenFASOC has been built on top of OpenROAD for push-button layout generation as part of the current open source effort. This talk will go through a few of our open-source analog generators (Temperature Sensor, Switched-Cap DC-DC,.. ), our implemented designs in Google's free shuttles MPW-I / II and our GF12LP tapeout of the OpenTitan SoC which heavily used open source tooling.

With a design that support a memory footprint up to 2 Petabytes ( with memory inception ) the Power 10 is the premier processor and platform for large in-memory database and big data applications. This talk will highlight the underlying technologies that enable this advantage, recent results and software developments that help enable an efficient in-memory approach

The DOE Exascale Computing Project (ECP) Software Technology focus area is developing an HPC software ecosystem that will enable the efficient and performant execution of exascale applications. Through the Extreme-scale Scientific Software Stack (E4S) [https://e4s.io], it is developing a comprehensive and coherent software stack that will enable application developers to productively write highly parallel applications that can portably target diverse exascale architectures. E4S provides both source builds through the Spack platform and a set of containers that feature a broad collection of HPC software packages. E4S exists to accelerate the development, deployment, and use of HPC software, lowering the barriers for HPC users. It provides Spack build cache for package binaries, container images, build manifests, and turn-key, from-source builds of popular HPC software packages developed as Software Development Kits (SDKs). This effort includes a broad range of areas including programming models and runtimes (MPICH, Kokkos, RAJA, OpenMPI), development tools (TAU, HPCToolkit, PAPI), math libraries (PETSc, Trilinos), data and visualization tools (Adios, HDF5, Paraview), workflows (flex), and compilers (LLVM), all available through the Spack package manager. E4S supports OpenPOWER (ppc64le), x86_64, and aarch64 systems. It includes the TAU Performance System - a versatile performance profiling and tracing toolkit for HPC and AI/ML applications running on CPUs and GPUs. The combination of E4S and TAU provides a comprehensive environment for program development, deployment, and performance evaluation for HPC and AI/ML users.

Access and utilization of HPC resources through a combination of Open OnDemand and XDMoD. These tools both improve HPC access through familiar browser based tools and bring job performance metrics straight to users for code review.

This talk will focus on challenges and opportunities in designing middleware for HPC, AI (Deep/Machine Learning), and Data Science. For HPC, features and sample performance numbers of using the MVAPICH2 and MVAPICH2-GDR libraries on OpenPOWER platforms will be presented. For the AI (Deep/Machine Learning) domain, we will focus on MPI-driven solutions to extract performance and scalability for popular Deep Learning frameworks (TensorFlow and PyTorch) and large out-of-core models. MPI-driven solutions to accelerate data science applications like Dask will be highlighted.

This presentation is going to cover the special use case and demo It is all about data-driven solutions to our challenges which we have been facing. I will use IBM Db2 as the data store and leverage Db2's ML capabilities, including in-database ML stored procedures, and Python UDF. I will be showing the demo using the IBM OpenPOWER system running Linux and DB2

In the realm of High Performance Computing (HPC), where many fields are looking to make advancements in every component of their industry, many turn to new emerging technologies to really make the difference. These include high performance OpenPOWER CPUs, datacenter GP-GPUs, large memory footprints, and specialized FPGAs. However, moving towards and integration of these new technologies can often be prohibitive either due to cost, time, complexity, lack of support, or any combination of these issues. Seeking to drive industry and research through collaboration and openness around many of these technologies, we introduce the OpenPOWER HUB - a community centralized place for the enablement and porting to OpenPOWER. The OpenPOWER HUB is a place where open source projects can freely test the OpenPOWER platform and all its collaborative resources.

Provide the details of Hardware and Software available for developers and researchers to develop applications and tools on IBM POWER/OpenPOWER platform

IBM has put forth great effort in educating individuals on the benefits of running on Power. Two programs aligning with this educational mission are PSAI and the Power Developer eXchange.

PSAI, also known as the Power Systems Academic Initiative, is an internal IBM program designed to provide educators with the resources they need to teach in-demand IBM Power skills to students worldwide. This program has been around for quite some time. However, I and many others have recently focused on renovating the program to accommodate the continual shift we have seen towards online learning heavily implemented across all levels of education, but most prominently at the college and university levels. As our efforts to update the program continue, we are operating towards providing instructors with the following:
• Access to an extensive library of technical content
• Opportunities to engage with IBM Subject Matter Experts
• FREE access to course materials and a complementary testing environment
• Remote access to Power technologies and software
• Faculty education and support
• Students develop in-demand technology skills

The Power Developer eXchange, or PDeX, is an online community designed to provide developers with a platform that contains everything they need to continue the development of open source applications on IBM Power. Members are granted access to a robust set of educational assets, a form to collaborate with others, and a means of receiving communal support. This online community is open to everyone and provides students with the opportunity to further their education on Power by accessing community content, proposing questions in the discussion forum, and even authoring technical content they can publish on the community. Students can now be active participants in the development we hope to see on Power.

Heterogeneous computing platforms are continuously evolving as hardware vendors (Intel, AMD, NVIDIA etc.) are increasingly focusing on architectural innovations
targeting scientific computing applications. Consequently, GPU computing is no longer confined to a single vendor hardware and programming model. SYCL is becominga de facto standard for vendor agnostic heterogeneous computing. Upgrading CUDA code to standard C++ with SYCL makes the applications portable across a range of existing and evolving accelerators including Nvidia GPUs. In this talk, we will review the state-of-the-art in heterogeneous computing and the current status of vendor agnostic tools.

Design and development of OpenPOWER architecture-based indigenous system on chip for health care and industrial automation application named “Ananth.” SoC that is compliant to A2O core (OpenPOWER Processor core) connected to peripherals like SPI, I2C, PCIe, Ethernet, DDR3, Flash memories- NAND & NOR, DMA via on-chip bus AXI-4.