BEGIN:VCALENDAR VERSION:2.0 PRODID:-//pretalx//cfp.openpower.foundation// BEGIN:VTIMEZONE TZID:US/Central BEGIN:STANDARD DTSTART:20001029T020000 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10;UNTIL=20061029T070000Z TZNAME:CST TZOFFSETFROM:-0500 TZOFFSETTO:-0600 END:STANDARD BEGIN:STANDARD DTSTART:20071104T020000 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:CST TZOFFSETFROM:-0500 TZOFFSETTO:-0600 END:STANDARD BEGIN:DAYLIGHT DTSTART:20000402T020000 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=4;UNTIL=20060402T080000Z TZNAME:CDT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 END:DAYLIGHT BEGIN:DAYLIGHT DTSTART:20070311T020000 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:CDT TZOFFSETFROM:-0600 TZOFFSETTO:-0500 END:DAYLIGHT END:VTIMEZONE BEGIN:VEVENT UID:pretalx-summit2021-9NLPRC@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T090000 DTEND;TZID=US/Central:20211028T090500 DESCRIPTION:OPF Summit Welcome and Keynotes DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:OpenPOWER Summit Welcome - James Kulina URL:https://cfp.openpower.foundation/summit2021/talk/9NLPRC/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-CLCSGD@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T090500 DTEND;TZID=US/Central:20211028T092000 DESCRIPTION:Antmicro Keynote by Michael Gielda DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:Antmicro: Software-driven Hardware in the Data Center: LibreBMC\, R enode\, RowHammer Test Platform and more - Michael Gielda URL:https://cfp.openpower.foundation/summit2021/talk/CLCSGD/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-QZFWJK@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T092000 DTEND;TZID=US/Central:20211028T093500 DESCRIPTION:As the excitement around the promise of CXL builds\, industry i ncumbents have continued to rapidly innovate with their own proprietary co herent interconnect busses.\nThese developments only serve to confuse what our Industry Standard future landscape will look like. \nThis presentati on will showcase a potential path for CXL to flourish by existing alongsid e these proprietary busses without the processor companies having to sacri fice their proprietary solutions. \n\nThe presentation will conclude that the integration of CXL with an Industry Standard Near Memory bus will driv e CXLs rapid organic growth in a shared memory centric world. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:OpenCAPI Consortium: Strategies for CXL’s success in a world of p roprietary Coherent Busses - Allan Cantle URL:https://cfp.openpower.foundation/summit2021/talk/QZFWJK/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-9EQBLG@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T093500 DTEND;TZID=US/Central:20211028T095000 DESCRIPTION:The Open Hardware Diversity Alliance formed in August 2021 with a partnership between RISC-V\, Chips Alliance\, OpenPower Foundation\, We stern Digital\, and IBM with a mission to provide programs to encourage pa rticipation and support the professional advancement of women and underrep resented individuals in open source hardware.\nWe asked ourselves: \nWhy a re there few women and underrepresented individuals in the open hardware c ommunity?\nIs it because open hardware is hard to navigate? \nIs career pr ogression a mystery? \nIs it a lack of visibility of the talent in open ha rdware to the community?\nIn this presentation\, Kim will share informatio n about the Alliance\, what we have done\, what has worked\, and didn’t work\, and invite anyone interested to join us! This is an interactive pre sentation\, where Kim will also ask the audience to participate in the con versation. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:The Open Hardware Diversity Alliance: What it is\, why it’s here\ , and how you can get involved! - Kim McMahon URL:https://cfp.openpower.foundation/summit2021/talk/9EQBLG/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-XBPLEG@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T095000 DTEND;TZID=US/Central:20211028T100500 DESCRIPTION:This talk will explore the creation of an open source hardware ecosystem that is composed of many ingredients. The talk will look at dif ferent parts of the hardware ecosystem\, from baseline technology ingredie nts\, EDA tooling\, IP building blocks\, and implementation\, and how orga nizations such as CHIPS Alliance\, OpenPower\, and RISC-V International ar e working together to help make the vision a reality. The talk will also h ighlight the need to build a diverse and inclusive talent pool from the bo ttom up. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:CHIPS Alliance: Building an Open Source Hardware Ecosystem: From Fo undations to Rooftops - Rob Mains URL:https://cfp.openpower.foundation/summit2021/talk/XBPLEG/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-LQCA9Z@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T103000 DTEND;TZID=US/Central:20211028T111500 DESCRIPTION:The Matrix Multiply Assist (MMA) architecture introduced in POW ER10 is an important feature in AI acceleration.  This talk describes imp lementation of MMA support in AI libraries and frameworks and performance improvements in some of the workloads. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:AI acceleration in POWER10 - Rajalakshmi S URL:https://cfp.openpower.foundation/summit2021/talk/LQCA9Z/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-7WPYMR@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T103000 DTEND;TZID=US/Central:20211028T143000 DESCRIPTION:SoC in Hours - A Power Chat\n1. OpenPOWER - A matured ISA\n2. Art of System Building - Its Libre-SoC\n3. Microwatt in FPGA - A Rapid Flo w\n4. Tapeout Microwatt in a click\n5. Bug the SoC - A Fire test DTSTAMP:20260309T150957Z LOCATION:RoomD SUMMARY:SoC in Hours - A Power Chat - MANIKANDAN NAGARAJAN\, Vinod Bussa\, Dr. Sumalatha\, Abhishek Sharma\, Harinagarjun URL:https://cfp.openpower.foundation/summit2021/talk/7WPYMR/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-QJWFH7@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T103000 DTEND;TZID=US/Central:20211028T111500 DESCRIPTION:System on Chip (SoC) is increasingly driving embedded and IoT d evices due to its\nability to tightly integrate microprocessors\, microcon trollers\, and peripherals. Moreover\,\nhardware accelerators are being us ed widely in machine learning in the form of SoCs to improve\nperformance and reduce energy consumption. In this presentation\, we will talk about t he course\nwe designed with multiple goals. First\, we want to introduce a nd build a community for POWER\nISA architecture. Second\, to bridge the g ap between the academic and industry that prevails in\nthe SoC design and verification. The course is designed in collaboration between NIE\, SASTRA \nUniversity\, SRM University\, JNTU Ananthapur\, IIT Guwahati and Object Automation Solutions and IBM. The course covers SoC design with Libre-So C toolchain\nand System Verilog\, IP verification\, SoC verification\, and application development. Initially\, the developed SoC design is implemen ted in FPGA (Field Programmable Gate Array). Testing\nprocedures are appli ed over it to make a front-end design flow familiar to the learner. The\nd eveloped SoC is subjected to the backend tool flow\, which covers open sou rce tools to convert\nthe design into a GDS II file. This course includes the contents needed to have hands-on\nexperience right from the understand ing of OpenPOWER architecture to GDS II generation required for chip tap-o ut in both design and test perspectives. DTSTAMP:20260309T150957Z LOCATION:RoomC SUMMARY:OpenPOWER ISA curriculum - Abhinandan S P URL:https://cfp.openpower.foundation/summit2021/talk/QJWFH7/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-RSEZGH@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T103000 DTEND;TZID=US/Central:20211028T111500 DESCRIPTION:The disaggregation of system resources promises various benefit s\, such as an increased flexibility of provisioning\, better consolidatio n of workloads\, and higher limits for bursts of resource consumption.\nSi milarly to how storage in the datacenter tends to be combined into large p ools to be shared across different machines\, portions of main memory coul d be disaggregated and made available on demand as well.\nThis could have the potential of making memory disaggregation a bulding block of the futur e datacenter.\nWith Memory Inception\, a disaggregation technology is anno unced for Power 10 systems\, and an OpenCAPI-based prototype – ThymesisF low – is already available.\nIn this talk\, we will outline our experime ntal setup using two IC922 Power 9 machines connected with ThymesisFlow\, as well as present a selection of the projects currently running in our la b that use this technology.\nIn particular\, we will discuss what new chal lenges arise for scale-up workloads such as In-Memory Databases and show e arly measurements with Hyrise\, an open source In-Memory Database develope d for research. DTSTAMP:20260309T150957Z LOCATION:RoomB SUMMARY:Beyond Machine Boundaries: Experience with Memory Disaggregation - Andreas Grapentin\, Felix Eberhardt URL:https://cfp.openpower.foundation/summit2021/talk/RSEZGH/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-JLQKUK@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T111500 DTEND;TZID=US/Central:20211028T120000 DESCRIPTION:The TAU Performance System is an open source toolkit for parall el performance measurement and analysis target to high-performance computi ng (HPC) and enterprise systems. Developed at the University of Oregon\, TAU has been ported to POWER systems for many years and is fully supported on the latest POWER processors. The talk will introduce the TAU technolo gies and showcase performance analysis and optimization outcomes for appli cations running on POWER platforms. It will cover the latest features of TAU and future directions\, especially with respect to opportunities for e nterprise use. DTSTAMP:20260309T150957Z LOCATION:RoomB SUMMARY:The TAU Performance System - Allen D. Malony URL:https://cfp.openpower.foundation/summit2021/talk/JLQKUK/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-98PTGG@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T111500 DTEND;TZID=US/Central:20211028T120000 DESCRIPTION:The teaching of the inter-related areas of computer architectur e\, computer organization\, and computer systems is at a crossroads\, one that could lead to another pedagogical (r)evolution. The first revolution occurred in the early 1990s\, spurred by research in the 1980s that re-vis ited RISC architectures and resulting in the seminal book entitled "Comput er Architecture: A Quantitative Approach" in 1989 and its subsequent prequ el book entitled "Computer Organization and Design: The Hardware/Software Interface" in 1993\, both centered around the MIPS instruction set archite cture (ISA). By the 2000s\, many institutions in higher education transiti oned their traditional course on operating systems concepts to a hands-on computer systems curriculum based on the CISC x86-64 ISA\, as captured by the seminal book entitled "Computer Systems: A Programmer’s Perspective. " While these books have served as exemplars for their respective areas\, one might argue that the use of disparate ISAs – MIPS versus x86-64 – serves as an unnecessary learning impediment and source of confusion. A po tential solution to this problem would be to align the teaching of all the se inter-related areas with the MIPS ISA entirely or x86-64 ISA entirely\; however\, the former has limited real-world deployment while the latter i s closed (and unnecessarily complex\, i.e.\, CISC). In contrast\, the POWE R architecture is open source and enjoys widespread deployment\, including two of the fastest supercomputers in the world (i.e.\, Sierra at Lawrence Livermore National Lab and Summit at Oak Ridge National Lab). For these r easons\, we envision a vertically integrated curriculum from hardware to s ystems software based on the POWER instruction set architecture. DTSTAMP:20260309T150957Z LOCATION:RoomC SUMMARY:A Vision for Transforming 21st-Century Pedagogy via Open Standards: OpenPOWER - Wu Feng URL:https://cfp.openpower.foundation/summit2021/talk/98PTGG/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-QTD73D@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T111500 DTEND;TZID=US/Central:20211028T120000 DESCRIPTION:ABSTRACT: Forest fires are on the increase worldwide. Forest fi res are a threat to our environment because they spread quickly and can bu rn down acres of lush forest if they are not attended to. Forest fires occ ur due to various reasons. As climate changes continue and temperatures in crease by a few degrees every year\, the forest fire will increase also. T rees that took many years to grow disappear in a very short time because o f fires\, leaving mountain areas barren\, no longer providing protection f rom rains and mudslides following those rains\, no longer providing oxygen clean air and shelter and food for birds and animals. \nUsually the fores t fires originate very discreetly and rangers are notified about the fire until it’s too late. This is because fire occur in dense forests where humans can’t possibly pose a challenge for the rangers. So\, to overcome this problem we will use Drones to navigate into the thick part of the fo rest and integrate Computer Vision into this by utilizing a state-of-the-a rt Convolutional Neural Network (CNN) to achieve the task. The entire proc ess is treated as classification task where the deep neural network model is responsible for classifying whether it's fire or non-fire from the imag e provided by the camera which is attached to the drone we deployed. The t raining is performed over a dataset containing both fire and non-fire imag es\, collected from various sources. \n\nKEYWORDS: Enterprise AI\, POWER9\ , AC922\, Deep Learning(DL)\, Neural Network.\n\nPROPOSED SYSTEM: We will develop the proper neural network architecture for the problem based on th e data and the goal set. Using a large set of data obtained from various r esources and department of forestry\, we will train the neural network to provide the most optimal strategy. Using the test data\, we will test the neural network for its ability to provide the optimal strategy. We will use the forest fires of that year and have the domain experts to verify th e optimality of the neural network’s strategy. Proposed models are very complicated\, and require intrinsic knowledge about specific programming l anguages and tools. Setting up the system for DL model is difficult. Pers onal systems lack computational powers\, which restricts the capabilities of DL models. Hence\, a need for on Premise based DL servers are required to help a large mass of people. To meet this need\, IBM has revealed Powe r9 processor\, the AC922 Power systems server\, designed for computing hea vy artificial intelligence workloads. \nTo provide up to 5.6 times the ban dwidth for data-intensive workloads\, the AC922 Power server incorporates next-generation I/O architectures such as PCle Gen4\, CAPI2.0\, OpenCAPI and Nvidia NVLINK. We use this server to train our model and optimize ou r performance in an efficient way. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:Next-gen Dynamic UAV using Power9 Systems - Deepthi\, Adithya Gopan \, Sri Kamani\, Sashank\, Barat. T URL:https://cfp.openpower.foundation/summit2021/talk/QTD73D/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-TNA77T@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T121500 DTEND;TZID=US/Central:20211028T130000 DESCRIPTION:IBM Bayesian Optimization Accelerator (BOA) is a global optimiz ation toolkit which applies machine learning techniques to solve some chal lenges arising from many practical engineering and designing problems: com putational or experimental simulations of the sampling space is very expen sive\; the objective functions have multiple local optima\; the collected data are noisy and do not have derivatives or analytic forms. Other featur es of BOA include batch sampling\, parameter analysis\, extensive implemen tations of kernel functions\, acquisition functions and optimization techn iques. The solution is integrated as an appliance which can be easily hook ed to existing High Performance Computing (HPC) or enterprise environment of different Operating Systems. In this talk\, we will discuss how BOA wor ks with existing HPC environment to get the optimization done. How to writ e interface functions to connect BOA with external workload to be optimize d. We will also present some use case studies which show performance gains against some traditional methods such as grid search and random search. DTSTAMP:20260309T150957Z LOCATION:RoomB SUMMARY:IBM Bayesian Optimization Accelerator - Xinghong He URL:https://cfp.openpower.foundation/summit2021/talk/TNA77T/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-MZ3GTQ@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T121500 DTEND;TZID=US/Central:20211028T130000 DESCRIPTION:Large-scale streaming and big data applications requiring large amounts of memory have made the OpenCAPI technology and FPGA an appealing and cost-effective solution. Large research labs to data analytic startup s are increasingly utilizing the technology to accelerate their applicatio ns creating new jobs and research opportunities. In this presentation we w ill discuss about the course that we designed to teach high performance an alysis of big data leveraging the FPGA technology together with OpenCAPI. DTSTAMP:20260309T150957Z LOCATION:RoomC SUMMARY:A course on Accelerating Big Data Analytics Application with FPGA a nd OpenCAPI to Improve the Reach out - Arghya Kusum Das\, Dr. Peter Hofste e URL:https://cfp.openpower.foundation/summit2021/talk/MZ3GTQ/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-8ZQCNE@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T121500 DTEND;TZID=US/Central:20211028T130000 DESCRIPTION:In the recent days\, Machine Learning & Neural Networks also fr eely referred to as Artificial Intelligence has grown so rapidly that it i s no more a system used only by Researchers in Universities\, but\, has ev olved so much that it is now actually deployed at Enterprise level across Organizations for their Production environment to analyse the data & gathe r meaningful insights from it. Many industries and organizations that have incorporated AI into its infrastructure have gained a competitive edge co mpared to their peers & this happening across industries. With AI in indus tries helping organizations building solutions for the betterment of the i ndustries in an efficient way\, employees can focus on things such as comm unicating and strategizing to build solutions that solve problems that is otherwise side-lined. With the advancement in Technology\, Companies are c ontinuously embedding more & more powerful resources in the chips so they can process complex & resource heavy Big Data\, Cloud & AI Applications. T he latest chips being open-sourced also paves the way for running Enterpri se AI Applications. One such great example is IBM POWER9 system which addr esses complex workloads such as Cognitive & Enterprise AI Applications. Th e POWER9 systems with its high powered GPUs help organizations manage thei r data on transactional information & Product feature that can be easily a nalyzed & get insights with the Machine Learning (ML)/Deep Learning (DL) M odels. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:AI APPLICATIONS ON POWER9 SYSTEM - Vaibhav Raja\, Sridhar Ramasubra manian URL:https://cfp.openpower.foundation/summit2021/talk/8ZQCNE/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-Z8G3BL@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T130000 DTEND;TZID=US/Central:20211028T134500 DESCRIPTION:Understanding machine learning algorithm is essential but the d evelopment\, acceleration\, and production engineering capabilities are al so required in industry. This machine learning course introduces students to the concepts of data preprocessing\, algorithmic overview of different supervised and unsupervised learning techniques\, their development strate gies and accelerating those algorithms using different hardware such as\, IBM Power hardware. We developed the course in collaboration with experts from different industries (e.g.\, Facebook and IBM). The course will help the community to know more about the capabilities of IBM POWER processor w hile Design an ML production system end-to-end including project scoping\, data needs\, modeling strategies\, and deployment requirements. DTSTAMP:20260309T150957Z LOCATION:RoomC SUMMARY:A Course on Machine Learning for Software Developers - Arghya Kusum Das URL:https://cfp.openpower.foundation/summit2021/talk/Z8G3BL/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-PYKVZA@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T130000 DTEND;TZID=US/Central:20211028T134500 DESCRIPTION:ANANTH is a type of Fabless SoC (System on Chip) designed and d eveloped at VLSI labs\, Electronics and Communication Engineering Departme nt\, JNTUA college of engineering\, Anantapur\, Under academic collaborati on with Open Power foundation and International Business Machines (IBM) In c. This is a fabless SoC built around IBM POWER A2O CORE and also has peri pherals like AMBA AXI\, SPI\, I2C\, ETHERNET\, NAND\, NOR\, DMA\, PCIe\,DD R3. This is indigenously developed for academic R&D purposes. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:ANANTH Fabless SoC - A C Venkatesh\, Unnamed user URL:https://cfp.openpower.foundation/summit2021/talk/PYKVZA/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-NWMQTE@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T130000 DTEND;TZID=US/Central:20211028T134500 DESCRIPTION:Advanced Cray-style Vectors are being developed for the Power I SA\, as a\nDraft Extension for submission to the new OpenPOWER ISA Working Group\,\nnamed SVP64. Whilst in-place Matrix Multiply was planned for a much\nlater advanced version of SVP64\, an investigation into putting FFMP EG's\nMP3 CODEC inner loop into Vectorised Assembler resulted in such a la rge\ndrop in code size (over 4x reduction) that it warranted priority\ninv estigation.\n\nDiscrete Cosine Transform (DCT)\, Discrete Fourier Transfor m (DFT)\nand Number-Theory Transform (NTT) form the basis of too numerous\ nhigh-priority algorithms to count. Normal SIMD Processors and even\nnorm al Vector Processors have a hard time dealing with them: inspecting\nFFMPE G's source code reveals that heavily optimised inline assembler (no\nloops \, just hundreds to thousands of lines of assembler) is not uncommon.\n\nT he focus of this NLnet-sponsored research is therefore to create enhanceme nts\nto SVP64 to be able to cover DFT\, DCT\, NTT and Matrix-Multiply enti rely\nin-place. In-place is crucially important for many applications (3D \, Video)\nto keep power consumption down by avoiding register spill as we ll as L1/L2\ncache strip-mining. General-purpose RADIX-2 DCT and complex DFT will be\nshown and explained\, as well as the in-place Matrix Multiply which does\nnot require transposing or register spill for any sized (incl uding non-power-of-two)\nMatrices up to 128 FMACs. The basics of SVP64\, covered in the Overview [1]\, will also\nbe briefly described.\n\n[1] http s://libre-soc.org/openpower/sv/overview/ DTSTAMP:20260309T150957Z LOCATION:RoomB SUMMARY:Draft SVP64 in-place Matrix Multiply and FFT / DCT for OpenPOWER - Luke Leighton URL:https://cfp.openpower.foundation/summit2021/talk/NWMQTE/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-SF8YLK@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T140000 DTEND;TZID=US/Central:20211028T144500 DESCRIPTION:Sorbonne Université\, in collaboration with Chips4Makers and LibreSOC are\nworking to provide a complete FOSS toolchain to make ASICs in mature\ntechnological nodes\, that is\, no smaller than 130nm. We take a circuit\ndescription in HDL\, synthetize with Y osys but instead of targeting a FPGA\, use\nan ASIC standard cell library to get the RTL description. From there\, with\nCoriolis2\, we perfor m the classical steps of a RTL to GDSII flow\, that is\,\nplacement\, routage along with very basic timing closure. One key feature is\nthat all the tools of the chain cooperate together directly in memory\, and ev en\nshare their underlying data-structures. The toolchain have been succ essfully\nused to build the first LibreSOC chip in TSMC 180nm that is currently under\nfabrication. The need for low cost or no-cost ASIC tool chain is increasing as\nfoundries\, like Skywater\, start to suppres s the NDA on their mature\ntechnological nodes (like Sky130).\n\nHDL : Hardware Description Language\, such as Verilog\, VHDL\, nMigen or Chise l.\n\nRTL: Register Transfert Logic\, the design expressed in term on 1-bi t DFFs\n and basic logic gates\, like NOR2\, NAND2\, XOR2\, ...\n\nGDS II: Graphic Design System version 2. The de-facto standard to send the\n layout a an ASIC design to any foundry.\n\n\nChips4Makers: https://ch ips4makers.io/\n\nLibreSOC: https://libre-soc.org/\n\nCoriolis2: https://c oriolis.lip6.fr/ DTSTAMP:20260309T150957Z LOCATION:RoomC SUMMARY:Coriolis2 -- A FOSS RTL to GDSII toolchain - Jean-Paul Chaput URL:https://cfp.openpower.foundation/summit2021/talk/SF8YLK/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-9C8NZZ@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T140000 DTEND;TZID=US/Central:20211028T144500 DESCRIPTION:The DOE Exascale Computing Project (EC) Software Technology foc us area\nis developing an HPC software ecosystem that will enable the effi cient\nand performant execution of exascale applications. Through the\nExt reme-scale Scientific Software Stack (E4S)\, it is developing a\ncomprehen sive and coherent software stack that will enable application\ndevelopers to productively write highly parallel applications that can\nportably targ et diverse exascale architectures - including the IBM\nOpenPOWER with NVID IA GPU systems. E4S features a broad collection of\nHPC software packages including the TAU Performance System(R) for\nperformance evaluation of HPC and AI/ML codes. E4S provides a curated set of packages\nbuilt using the Spack package manager and provides both bare-metal installation and \ncont ainerized distributions that feature a broad collection of HPC\nsoftware packages. E4S exists to accelerate the development\, deployment\,\nand us e of HPC software\, lowering the barriers for HPC users. DTSTAMP:20260309T150957Z LOCATION:RoomB SUMMARY:E4S: Extreme-scale Scientific Software Stack - Sameer Shende URL:https://cfp.openpower.foundation/summit2021/talk/9C8NZZ/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-C9Q3GS@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T140000 DTEND;TZID=US/Central:20211028T144500 DESCRIPTION:Memory is an extremely important part of solutions and the memo ry controller is the interface between external memory and your system – it can have consequences for everything from performance\, reliability\, to even security! \n\nThis has been shown by the work Google has been fund ing to demonstrate [new RowHammer exploits](https://security.googleblog.co m/2021/05/introducing-half-double-new-hammering.html) found using a fully open source\, [FPGA based memory platform](https://antmicro.com/blog/2021/ 04/lpddr4-test-platform/) and [controller](https://github.com/enjoy-digita l/litedram) (paired with [open source tooling](https://symbiflow.github.io /)).\n\nNow using our [experience optimizing](https://research.google/pubs /pub50436/) [full system performance](https://research.google/pubs/pub5037 0/) [through changes](https://research.google/pubs/pub49145/) [to the memo ry subsystems](https://research.google/pubs/pub50436/) (through things lik e tcmalloc)\, we plan to drive changes in the memory controller space. As part of this effort we are now planning to build silicon to verify this wo rk including at advance nodes with our partners like IBM\, Antmicro and th e CHIPS Alliance. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:A fully open source memory controller targeting LPDDR4/5 for FPGA a nd ASIC use cases - Tim 'mithro' Ansell URL:https://cfp.openpower.foundation/summit2021/talk/C9Q3GS/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-F9DKAK@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T144500 DTEND;TZID=US/Central:20211028T153000 DESCRIPTION:We expect before the end of 2021 to see the life of three proto types of the Open Hardware GNU/Linux PowerPC Laptop. The project started i n late 2014\, after a brief summary of the previous episodes and the lates t update regarding the prototypes trough the recent electronics shortage a nd increase of the costs. We disclose how you can take part on the pre-pro duction run. This difficult project\, under an uncertainly period 2015-202 1 to design a Power Architecture notebook\, how is inserted in the const ellation of an Open Hardware Power Architecture computing switch. As this is a Community Driven open hardware power architecture project we see how you can be a protagonist of this switch. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:Prepare yourself to switch computing to Open Hardware Power Archite cture - Roberto Innocenti URL:https://cfp.openpower.foundation/summit2021/talk/F9DKAK/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-EVXEPV@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T144500 DTEND;TZID=US/Central:20211028T153000 DESCRIPTION:Everything is changing. From Healthcare to Automotive markets w ithout forgetting the Financial markets or any type of Engineering. Everyt hing has stopped being created by an individual in a single computer or be st case scenario a small team in a coupe of computers to something that is being developed and perfectioned by the use of HPC and AI\, involving all kind of different people with different skills all around the world.\nEve n AI is something that we no longer run in a single computer\, no matter h ow powerful it is. What drives everything today is HPC or High Performance Computing. This can help develop better Healthcare\, better Automobiles\, better Financials and better anything that we run on them.\nIn this sessi on we will introduce the IBM Power architecture\, HPC supercomputers\, the ir differential SW solutions and will run a small demo in the IBM Cloud Pa k for data. DTSTAMP:20260309T150957Z LOCATION:RoomB SUMMARY:Differential Software Solutions on HPC and IBM Power Architecture - Ander Ochoa Gilo URL:https://cfp.openpower.foundation/summit2021/talk/EVXEPV/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-SQCTSQ@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T144500 DTEND;TZID=US/Central:20211028T153000 DESCRIPTION:Artificial Intelligence (AI) is a powerful science that utilize s sufficient\nmethodologies\, strategies\, and systems to take care of uns olvable real-world issues.\nThere is a wide range of technological advance ments and research is going on to\nsolve many real-time problems with rega rds to all different aspects of today’s society.\nRecent years have witn essed significant advances in geospatial artificial intelligence\n(GeoAI)\ , which is the integration of geospatial studies and AI\, especially machi ne\nlearning and deep learning methods and the latest AI technologies in b oth academia\nand industry. Setting up AI-based machines in solving geospa tial applications\nrequires a high amount of computing. With processors li ke IBM POWER9\, we can\naddress complex workloads with a huge amount of da ta while data visualization\,\nstatistical analysis\, pattern recognition\ , and inference building in a very fast and\nefficient manner. Thus combin ing H2O driverless AI and IBM power systems for\nenabling geospatial appli cations to harness AI for competitive gain. DTSTAMP:20260309T150957Z LOCATION:RoomC SUMMARY:Geo-AI applications using H2O.ai on IBM open POWER 9 systems - Baga vathy Priya URL:https://cfp.openpower.foundation/summit2021/talk/SQCTSQ/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-GLZJVY@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T144500 DTEND;TZID=US/Central:20211028T153000 DESCRIPTION:Baseboard management controllers (BMCs) sit at the heart of the boot and control infrastructure in the datacenter\, so they require a uni que functionality set. Based on work to improve open source FPGA tooling\ , it’s now possible to replace traditional BMC ASICs with soft processor s running on low cost FPGA hardware while still running the familiar OpenB MC software stack. To demonstrate this\, the LibreBMC project was created and is being run under the OpenPOWER Foundation. Taking advantage of OCP ’s DC-SCM spec\, Antmicro has created the first ever open source DC-SCM 1.0 modules with LibreBMC supported FPGAs. This allows drop in replacement on existing designs\, fully verifiable hardware\, and the unique opportun ity to do software style deployment of new “hardware based” security f eatures (like memory tagging) even after hardware has been deployed in the datacenter! DTSTAMP:20260309T150957Z LOCATION:RoomD SUMMARY:Introduction to the LibreBMC project - Todd Rosedahl URL:https://cfp.openpower.foundation/summit2021/talk/GLZJVY/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-PNJTAX@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T153000 DTEND;TZID=US/Central:20211028T154500 DESCRIPTION:Toshaan Bharvani\, as the TSC of the OpenPOWER Foundation will go through the working groups and their activities during the past year. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:OpenPOWER Working Groups Walkthrough - Toshaan Bharvani URL:https://cfp.openpower.foundation/summit2021/talk/PNJTAX/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-QALSZW@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T160000 DTEND;TZID=US/Central:20211028T164500 DESCRIPTION:coreboot is open source firmware development framework that pow ers more then\n10% of desktops\, laptops and workstations. It supports mul tiple architetcures:\nx86\, ARM\, ARM64\, RISC-V. Bringing it to OpenPOWER means introduction of\nestablished and sizable community\, diverse econom y of licensed service\nproviders as well as less complexity during new har dware integration.\n\nThis talk will present the progress of porting the P OWER9 architecture to\ncoreboot along with Talos II and Talos II Lite mach ines (FSF RYF certified).\nThis project became possible with the cooperati on of 3mdeb Embedded Systems\nConsulting and Insurgo Technologies Libres/O pen Technologies. We will present\nproblems and hardships encountered duri ng the work and other exciting stories\nwith the initial results of the fi rst hostboot code audit conducted as part of\nthe work. Finally\, we will present the current state of the booting process on\nTalos II using corebo ot. DTSTAMP:20260309T150957Z LOCATION:RoomC SUMMARY:coreboot on POWER9 - Piotr Król URL:https://cfp.openpower.foundation/summit2021/talk/QALSZW/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-BTAGDV@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T160000 DTEND;TZID=US/Central:20211028T161000 DESCRIPTION:To port Intel x86 intrinsic to OpenPower intrinsic\, we have to make testing framework. Porting must be accurate and without error or mis take. Test cannot be done by hand. It must be done automatically.\n In por ting process\, result must be same and it is indispensable. Performance mu st be good. Must be able to measure and compare latency and throughput. Th is testing framework will made by open source.\n This testing framework is executes both Intel x86 and OpenPower machine. Both is connected by netwo rk because both is not build on same machine.\n We cannot test all pattern so we generate random data to test. Input data both Intel x86 Systems and OpenPower Systems and check result value is equal.\nNetwork Module may be made by Python and Testing module may be made by C language extension of Python DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:Testing Framework to port and optimize SIMD library to OpenPOWER Sy stems - Daisuke Oka URL:https://cfp.openpower.foundation/summit2021/talk/BTAGDV/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-TM3JWX@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T160000 DTEND;TZID=US/Central:20211028T164500 DESCRIPTION:This talk will focus on high-performance and scalable middlewar e for MPI and DL applications on the OpenPOWER platform. The focus will be on three products with commercial support being available from X-ScaleSol utions. The first product focuses on the OSU MVAPICH2 MPI libraries and th eir capabilities for high-performance computing with both CPUs (OpenPOWER) and GPUs (NVIDIA). The second product focuses on tight integration betwee n the OSU MVAPICH2-GDR MPI library and the Horovod stack to provide high-p erformance and scalable Deep Learning (DL) with deep introspection (DI) ca pabilities for DL frameworks like TensorFlow and PyTorch. The DI capabilit ies allow DL users and runtime developers to easily optimize their DL appl ications on modern systems. The third product focuses on a high-performanc e and scalable checkpointing library for HPC and DL applications. Performa nce results from the ORNL SUMMIT system (#2nd) and Lassen (#20th) with tho usands of GPUs and POWER9 CPUs will be presented. DTSTAMP:20260309T150957Z LOCATION:RoomB SUMMARY:High-Performance and Scalable Middleware for HPC and Deep Learning on OpenPOWER Platforms - Donglai Dai\, Dhabaleswar K (DK) Panda URL:https://cfp.openpower.foundation/summit2021/talk/TM3JWX/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-GDVX7U@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T160000 DTEND;TZID=US/Central:20211028T164500 DESCRIPTION:TOY-SRAM\nRobert Montoye\nOctober 28 2021\nMicroprocessors use multiple high-speed multiport register files to improve their performance . In BOOM\, the high-performance RISC V\, the custom register file took as much design effort as the rest of the design. The TOY-SRAM\, open-source \, multi-port memory system is designed to replace custom circuit design w ith a simple set of choices for the fab and the system designer. For the chip fabrication facility\, it offers a canonical specification that can b e optimized for use in a wide variety of applications. The system design er can then select the desired fast\, low voltage friendly multiport memor y from a menu of choices. This talk will discuss plans on 130 nm 5LM silic on which eases prototyping into future fabs while making the 10T SRAM the high bandwidth voltage scalable memory cell and encouraging fabs on its de nsity. DTSTAMP:20260309T150957Z LOCATION:RoomD SUMMARY:The Toy-SRAM Project - Robert Montoye URL:https://cfp.openpower.foundation/summit2021/talk/GDVX7U/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-PAS3TZ@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T161000 DTEND;TZID=US/Central:20211028T162000 DESCRIPTION:We aim to bring togheter a group of people that is interested i n the hardware that they use to build the platform of the future. There ar e a lot of SBC that are very affordable and performing but none of them ar e based on Power architecture.\nI started in december 2020 to design the D jango0's schematic\, a SBC based on the last (in 2020) accessible low powe r Power Based CPU\, the NXP T1040\, but unfortunately it has a loss in ter ms of cost/performance\, in relation with competitors.\nThe actual Django design is slowly turning in a proof of concept\, but what we want to suppo rt is the knowledge of the requested know-how that can be reused for upcom ing power architectures\, and make it open and available to all the commun ity.\nWe want to be ready for the next Open Power step! DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:Open Hardware through Open Power SBC - Manuel Virgilio URL:https://cfp.openpower.foundation/summit2021/talk/PAS3TZ/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-R8EHYR@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T162000 DTEND;TZID=US/Central:20211028T163500 DESCRIPTION:Toshaan Bharvani the OpenPOWER Technical Steering Committee cha ir will be presenting the new suite of tools that OpenPOWER Foundation is using for collaboration and engagement with the OpenPOWER ecosystem. The f oundation is adopting open source tools and collaboration platforms typica l of other open source projects to expand community reach and drive engage ment. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:OpenPOWER Collaboration Walkthrough - Toshaan Bharvani URL:https://cfp.openpower.foundation/summit2021/talk/R8EHYR/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-YK8NLU@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T164500 DTEND;TZID=US/Central:20211028T173000 DESCRIPTION:The industry has begun to reconfigure the standard memory topol ogy\, and these new configurations promise to make computing systems bette r than ever. Enormous pools of cache-coherent disaggregated “Far” mem ory will be made available to all processors\, even coprocessors\, and wil l be read and written using standard memory protocols no matter which proc essor accesses it. “Near” memory is set to move away from limiting DD R interfaces to support larger capacities at higher speeds while using les s energy to move data around. What will this do to computing system archi tecture? How will it be supported? Which applications will benefit the m ost? Will other systems use this approach outside of the realm of superco mputers? In this session a panel of distinguished industry participants w ill share their sometimes-contradictory/sometimes-controversial views on t hese questions and more as the audience learns that there are many alterna tives vying to win out in this space. DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:Panel: A Complete Re-Think for Memory Configurations - Tanj Bennett \, Jim Handy\, Brian Allison\, Tom Coughlin URL:https://cfp.openpower.foundation/summit2021/talk/YK8NLU/ END:VEVENT BEGIN:VEVENT UID:pretalx-summit2021-AXKD8F@cfp.openpower.foundation DTSTART;TZID=US/Central:20211028T173000 DTEND;TZID=US/Central:20211028T173500 DESCRIPTION:OpenPOWER Closing DTSTAMP:20260309T150957Z LOCATION:RoomA SUMMARY:OpenPOWER Summit 2021 Closing Remarks - James Kulina URL:https://cfp.openpower.foundation/summit2021/talk/AXKD8F/ END:VEVENT END:VCALENDAR