OpenPOWER Summit 2021

OpenPOWER ISA curriculum
2021-10-28, 10:30–11:15, RoomC

System on Chip (SoC) is increasingly driving embedded and IoT devices due to its
ability to tightly integrate microprocessors, microcontrollers, and peripherals. Moreover,
hardware accelerators are being used widely in machine learning in the form of SoCs to improve
performance and reduce energy consumption. In this presentation, we will talk about the course
we designed with multiple goals. First, we want to introduce and build a community for POWER
ISA architecture. Second, to bridge the gap between the academic and industry that prevails in
the SoC design and verification. The course is designed in collaboration between NIE, SASTRA
University, SRM University, JNTU Ananthapur, IIT Guwahati and Object Automation Solutions and IBM. The course covers SoC design with Libre-SoC toolchain
and System Verilog, IP verification, SoC verification, and application development. Initially, the developed SoC design is implemented in FPGA (Field Programmable Gate Array). Testing
procedures are applied over it to make a front-end design flow familiar to the learner. The
developed SoC is subjected to the backend tool flow, which covers open source tools to convert
the design into a GDS II file. This course includes the contents needed to have hands-on
experience right from the understanding of OpenPOWER architecture to GDS II generation required for chip tap-out in both design and test perspectives.

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I am an Associate Professor at NIE