2021-10-28, 14:00–14:45 (US/Central), RoomC
Sorbonne Université, in collaboration with Chips4Makers and LibreSOC are
working to provide a complete FOSS toolchain to make ASICs in mature
technological nodes, that is, no smaller than 130nm. We take a circuit
description in HDL, synthetize with Yosys but instead of targeting a FPGA, use
an ASIC standard cell library to get the RTL description. From there, with
Coriolis2, we perform the classical steps of a RTL to GDSII flow, that is,
placement, routage along with very basic timing closure. One key feature is
that all the tools of the chain cooperate together directly in memory, and even
share their underlying data-structures. The toolchain have been successfully
used to build the first LibreSOC chip in TSMC 180nm that is currently under
fabrication. The need for low cost or no-cost ASIC toolchain is increasing as
foundries, like Skywater, start to suppress the NDA on their mature
technological nodes (like Sky130).
HDL: Hardware Description Language, such as Verilog, VHDL, nMigen or Chisel.
RTL: Register Transfert Logic, the design expressed in term on 1-bit DFFs
and basic logic gates, like NOR2, NAND2, XOR2, ...
GDSII: Graphic Design System version 2. The de-facto standard to send the
layout a an ASIC design to any foundry.
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Jean-Paul Chaput holds a Master Degree in MicroElectronics and Software
Engineering. He joined the LIP6 laboratory within SU (formerly UPMC) in 2000.
Currently he is a Research Engineer in the Analog and Mixed Signal
Team at LIP6. His main focus is on physical level design software. He is a
key contributor in developing and maintaining the Alliance/Coriolis VLSI
CAD projects for CMOS technologies. In particular he contributed in
developing the routers of both Alliance/Coriolis and the whole Coriolis
toolchain infrastructure. He his now a key contributor in extending
Alliance/Coriolis to the Analog Mixed-Signal integration for nanometric