A research scholar in the field of Front end VLSI Design Verification and an industry expert as ASIC/ SoC Design Verification Architect with strong experience in System Verilog, Verilog & UVM (Universal Verification Methodology. Developed multiple SoC level Test bench Architectures from the scratch for many complex designs across the domains. Has vast experience in FPGA, ASIC & SoC Design & Verification Life Cycles.
SoC in Hours - A Power Chat
1. OpenPOWER - A matured ISA
2. Art of System Building - Its Libre-SoC
3. Microwatt in FPGA - A Rapid Flow
4. Tapeout Microwatt in a click
5. Bug the SoC - A Fire test