OpenPOWER Summit 2021

SoC in Hours - A Power Chat
2021-10-28, 10:30–14:30, RoomD

SoC in Hours - A Power Chat
1. OpenPOWER - A matured ISA
2. Art of System Building - Its Libre-SoC
3. Microwatt in FPGA - A Rapid Flow
4. Tapeout Microwatt in a click
5. Bug the SoC - A Fire test

This is a tutorial to make a System on Chip in a few hours. This completely covers OpenPOWER based SOC design flow right from the OpenPOWER ISA to GDS II tapeout file generation, surprisingly within a few hours.
The additional feature is that this tutorial also covers testing of SoC, which most of the events less concentrate on.

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He is an enthusiastic engineer with the aspiration of electronics engineering and Chip design. He has 11+ years of Industrial, research and academic experience. Currently conducting research on VLSI architecture for Domain Specific Applications at SASTRA University, India. Research interest includes Architecture development for computing platforms and System on Chip design. Exploring open source tools for chip making.

He is a passionate engineer in the field of embedded systems and IoT domains. He graduated in electronics and communication engineering from Motilal Nehru NIT Allahabad. Currently working as a Research scholar with Object Automations solutions ltd. He has worked in the field of Robotics, UASs development, and SOC design. Areas of interest include Machine learning, deep learning, and Soc design.

A research scholar in the field of Front end VLSI Design Verification and an industry expert as ASIC/ SoC Design Verification Architect with strong experience in System Verilog, Verilog & UVM (Universal Verification Methodology. Developed multiple SoC level Test bench Architectures from the scratch for many complex designs across the domains. Has vast experience in FPGA, ASIC & SoC Design & Verification Life Cycles.