Brian Allison is an IBM Senior Technical Staff Engineer and Chief Engineer for External Engagements including CAPI and OpenCAPI. Over his 25 year career at IBM, Mr. Allison was the Chief Engineer of various industry leading IBM chip sets that spanned cache coherent, memory and node controllers. His expertise is in computer architecture and logic design. In his current role, Brian leads the IBM enablement team that drives partner led solutions including OpenCAPI in various ingress, egress, and CPU off-load transforms.
The industry has begun to reconfigure the standard memory topology, and these new configurations promise to make computing systems better than ever. Enormous pools of cache-coherent disaggregated “Far” memory will be made available to all processors, even coprocessors, and will be read and written using standard memory protocols no matter which processor accesses it. “Near” memory is set to move away from limiting DDR interfaces to support larger capacities at higher speeds while using less energy to move data around. What will this do to computing system architecture? How will it be supported? Which applications will benefit the most? Will other systems use this approach outside of the realm of supercomputers? In this session a panel of distinguished industry participants will share their sometimes-contradictory/sometimes-controversial views on these questions and more as the audience learns that there are many alternatives vying to win out in this space.