2021-10-28, 16:45–17:30, RoomA
The industry has begun to reconfigure the standard memory topology, and these new configurations promise to make computing systems better than ever. Enormous pools of cache-coherent disaggregated “Far” memory will be made available to all processors, even coprocessors, and will be read and written using standard memory protocols no matter which processor accesses it. “Near” memory is set to move away from limiting DDR interfaces to support larger capacities at higher speeds while using less energy to move data around. What will this do to computing system architecture? How will it be supported? Which applications will benefit the most? Will other systems use this approach outside of the realm of supercomputers? In this session a panel of distinguished industry participants will share their sometimes-contradictory/sometimes-controversial views on these questions and more as the audience learns that there are many alternatives vying to win out in this space.
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This is a panel of memory technical experts who will discuss the problem of memory interfaces. Today’s interfaces force both the memory chips and the processors that drive them to consume much more power than is necessary, thanks to the fact that the semiconductor industry has not abandoned older interfaces, but has instead simply adjusted them to run at higher speeds.
Memory interfaces also limit system architectures since memory is not easily shared between multiple processors. Once again, the memory interface was originally defined before today’s architectural advances were conceived, and the incremental updates that have been made to that interface are incapable of supporting today’s required configurations.
The panel will discuss how power consumption has become a memory issue and panelists will debate their opinions about how memory system architecture will change to overcome this issue. In a similar vein they will discuss the fact that disaggregation requires shared resources, and that memory is the last resource to be shared thanks to concerns about latency and coherency. Again, they will discuss and debate future solutions to memory disaggregation.
Discussions will cover newer technologies like OpenCAPI, OMI, CXL, and Gen-Z, along with more established approaches like DDR, PCIe, Shared Memory as I/O, and locally-focused coherency protocols.
Tanj Bennett (Avant-Gray LLC) has worked both on software and hardware. In the last decade he was software architect at Bing and then hardware architect at Azure. During his work in Azure his focus became the memory system since that has become the largest, hardest, and most expensive problem for the cloud. He now consults on topics related to system architecture, memory, and interfaces.
Jim Handy of Objective Analysis is a 35-year semiconductor industry executive and a leading industry analyst. Following marketing and design positions at Intel, National Semiconductor, and Infineon he became known for his technical depth, accurate forecasts, industry presence, and numerous market reports, articles, white papers, and quotes. He is frequently invited to speak and act as a panel moderator at trade events. He posts blogs at www.TheMemoryGuy.com, and www.TheSSDguy.com.
Brian Allison is an IBM Senior Technical Staff Engineer and Chief Engineer for External Engagements including CAPI and OpenCAPI. Over his 25 year career at IBM, Mr. Allison was the Chief Engineer of various industry leading IBM chip sets that spanned cache coherent, memory and node controllers. His expertise is in computer architecture and logic design. In his current role, Brian leads the IBM enablement team that drives partner led solutions including OpenCAPI in various ingress, egress, and CPU off-load transforms.
Tom Coughlin, President, Coughlin Associates is a digital storage analyst and business and technology consultant. He has over 40 years in the data storage industry with engineering and senior management positions at several companies. Coughlin Associates consults, publishes books and market and technology reports (including The Media and Entertainment Storage Report and an Emerging Memory Report), and puts on digital storage-oriented events. He is a regular storage and memory contributor for forbes.com and M&E organization websites. He is an IEEE Fellow, Past-President of IEEE-USA and is active with SNIA and SMPTE. For more information on Tom Coughlin and his publications and activities go to www.TomCoughlin.com.